1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming a semiconductor device, and more particularly to a method of forming a semiconductor memory, including a flash memory, and scaling of a memory using a common substrate structure, and to the structure resulting from the inventive method, including a floating gate on a back-plane.
2. Description of the Related Art
Non-volatile electrically erasable and programmable memory structures (EEPROMs), such as a flash memory, utilize a floating gate whose charging is controlled by appropriate biasing of the source, drain and controlling gate. A flash memory is unique in providing fast compact storage which is both nonvolatile and rewritable.
In a flash memory, the threshold voltage Vt for conduction of a field-effect transistor (FET) changes state depending upon the amount of charge stored in a floating gate (FG) part of the FET. The floating gate is a charge storing region which is isolated from a more traditional control gate (CG) (connected by "wordline") by a dielectric commonly based on silicon dioxide. The state of the Vt changes with the amount of charge stored by the FG.
The gate stack in such structures includes the silicon channel with an injection/tunneling oxide, the floating gate and a thicker control oxide with a controlling gate on top. They are usually designed for flash erase in a block, for writing by word, and derive a density advantage from their single transistor (element) structure.
Use of floating gates in memories have their origin in the earlier work of Kahng (e.g., see D. Kahng et al., "A Floating Gate and its Application to Memory Devices," Bell Systems Technical Journal, 46 1288 (1967)) who described a non-volatile MOS memory with a conducting metal layer interposed between the gate and the channel with oxide as a separating layer. This structure used tunneling, direct and indirect, without the use of hot carriers. The ideas behind this structure evolved to use of dielectrics in MNOS cells (e.g., See H. A. R. Wagener et al., "The Variable Threshold Transistor, A New Electrically Alterable Non-Destructive Read-Only Storage Device," Tech. Dig. of IEDM, Washington D.C. (1987)), use of hot carriers to inject into floating gate structures (e.g., see D. Frohmann-Bentchkowsky, "A Fully Decoded 2048-bit Electrically Programmable MOS-ROM" Tech. Dig. of ISSCC, 80 (1971)) and the more write-efficient structures with an external gate whose various forms are used today (e.g., see Iizuka et al., "Stacked Gate Avalanche Injection Type MOS (SAMOS) Memory", Tech. Dig. of 4th Conf. Sol. St. Dev., Tokyo (1972) and Japan J. of Appl. Phys., 42 158 (1973)).
These forms of electrically erasable and programmable memories include structures such as flash structures using NAND and NOR architectures. Most of these structures use various hot carrier injection processes.
FIGS. 1(A)-1(C) illustrate some different types of structures which such non-volatile memories may adopt, such as a floating gate with oxide injection (FLOTOX) using injection from the drain, erasable tunneling oxide (ETOX) using injection from the channel, and, source side injection (SISOS) using injection from the source using a field from a select gate. Being a single element structure, these structures have advantages in packing, and they have specific forms of unipolar or bipolar write, erase, and read cycles that are compatible with non-volatile operation.
However, only one form (e.g., the nano-crystal memory, as disclosed in U.S. Pat. Nos. 5,508,543 and 5,714,766, commonly assigned with the present application and incorporated herein by reference) may use direct tunneling with non-volatility. An example of this structure is shown in FIG. 1(D).
A further problem arises in that, as device sizes shrink, it becomes increasingly difficult to make these memory structures since the injection oxide and the control oxide cannot be shrunk because of charge leakage. This non-scalability of oxide thickness results in a larger (e.g., longer) electrical distance between the controlling gate and the channel than the gate length. The larger electrical distance makes integration and higher density more difficult, if not impossible. Additional consequences include read disturbance, poor transconductance and poor sub-threshold characteristics, and limited cyclability.
Moreover, an essential requirement of scaling of all field-effect-based structures is that all electrical distances must be scaled together simultaneously. In flash memory structures where the vertical stack has a physical thickness exceeding 47 nm (e.g., currently limited by the injection oxide thickness (greater than 7 nm), floating gate thickness (greater than 30 nm), and the control gate thickness (greater than 10 nm)), a constraint is placed on both minimum device size and voltages and power at which the devices are operable.